0.5-V 25-nm 6-T Cell with Boosted Word Voltage for 1-Gb SRAMs : Solid-State Circuit Design -Architecture, Circuit, Device and Design MethodologyKOTABE, Akira; ITOH, Kiyoo; TAKEMURA, Riichiro et al.IEICE transactions on electronics. 2012, Vol 95, Num 4, pp 555-563, issn 0916-8524, 9 p.Article

0.5-V Low-V_T CMOS Preamplifier for Low-Power and High-Speed Gigabit-DRAM ArraysKOTABE, Akira; YANAGAWA, Yoshimitsu; AKIYAMA, Satoru et al.IEEE journal of solid-state circuits. 2010, Vol 45, Num 11, pp 2348-2355, issn 0018-9200, 8 p.Conference Paper

A Low-V_t Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing : Solid-State Circuit Design -Architecture, Circuit, Device and Design MethodologyAKIYAMA, Satoru; TAKEMURA, Riichiro; SEKIGUCHI, Tomonori et al.IEICE transactions on electronics. 2012, Vol 95, Num 4, pp 600-608, issn 0916-8524, 9 p.Article

Fluctuation Tolerant Charge-Integration Read Scheme for Ultrafast DNA Sequencing with Nanopore Device : Solid-State Circuit Design -Architecture, Circuit, Device and Design MethodologyONO, Kazuo; YANAGAWA, Yoshimitsu; KOTABE, Akira et al.IEICE transactions on electronics. 2012, Vol 95, Num 4, pp 651-660, issn 0916-8524, 10 p.Article

1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput ComputingSEKIGUCHI, Tomonori; ONO, Kazuo; KOTABE, Akira et al.IEEE journal of solid-state circuits. 2011, Vol 46, Num 4, pp 828-837, issn 0018-9200, 10 p.Conference Paper

Random telegraph signal in flash memory: Its impact on scaling of multilevel flash memory beyond the 90-nm nodeKURATA, Hideaki; OTSUGA, Kazuo; KOTABE, Akira et al.IEEE journal of solid-state circuits. 2007, Vol 42, Num 6, pp 1362-1369, issn 0018-9200, 8 p.Article

A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage schemeKOTABE, Akira; OSADA, Kenichi; KITAI, Naoki et al.IEEE journal of solid-state circuits. 2005, Vol 40, Num 4, pp 870-876, issn 0018-9200, 7 p.Conference Paper

A 0.13-μm, 0.78-μm² low-power four-transistor SRAM cell with a vertically stacked poly-silicon MOS and a dual-word-voltage schemeKOTABE, Akira; OSADA, Kenichi; KITAI, Naoki et al.Symposium on VLSI Circuits. 2003, pp 60-63, isbn 0-7803-8287-0, 1Vol, 4 p.Conference Paper